1. Field of the Invention
The present invention relates to a method of estimating heat which is developed in a chip while designing a circuit, in order to improve the reliability of an LSI and the quality of a layout.
2. Description of the Background Art
The need to estimate heat which is developed in a semiconductor integrated circuit while designing the semiconductor integrated circuit has been noted in the art. This is because heat developed in the semiconductor integrated circuit could cause the semiconductor integrated circuit to operate beyond a predetermined operation condition. If this occurs, it is difficult to ensure that a signal operates at a normal timing.
The importance of power consumption in a chip is stressed in Japanese Patent Laid-Open Gazette No. 3-3348 (Specification, page 3, line 12 to page 4, line 1). The Gazette describes a technique of performing MIN-CUT method so that distribution of a consumption power is uniform in a chip (Specification, page 9, line 9 to page 10, line 4 and FIG. 2).
However, in this conventional technique, it is necessary to exchange cells between a plurality of divided areas. In addition, to exchange the cells, the positions of wire lines must be changed while considering a consumption power. This is not only labor-consuming but also time-consuming to realize.